Bengaluru: San Jose-based deeptech startup Mixx Technologies has acquired Bengaluru-based chip design firm Sophic Silicon Technologies and signed a three-year collaboration with Kaynes Semicon’s Sanand OSAT tobuild and operate advanced optical integrated circuit assembly and test capability for its products.
The companies did not disclose financial details of the transaction.
The acquisition gives Mixx access to critical mixed-signal design resources needed for its silicon photonics and co-packaged optics (CPO) platform, as it looks to tap India’s fast-growing AI infrastructure market, Mixx Technologies chief executive Vivek Raghuraman told ET.
Sophic Silicon founder Deepak Pancholi will join Mixx as vice president of IC design, Raghuraman said.
The 24-month-old semiconductor IP design startup’s large engineering team will continue to operate from India as Mixx looks to tap the country’s fast-growing AI infrastructure market.
Kaynes Semicon chief executive Raghu Panicker said the company’s collaboration with Mixx is focused on silicon photonics and co-packaged optics, areas that fall within the advanced packaging domain.
“If you look at the challenges being faced in data centres: data transfer, latency and the time taken, these can be addressed when data flows through optics,” he told ET.
Mixx is working on solving the connectivity challenges emerging in data centres, while Kaynes will support the company on the manufacturing side, Panicker said. “We will help them with manufacturing, assembly, testing and reliability for their product.”
The collaboration could help establish advanced semiconductor packaging capability for silicon photonics and co-packaged optics in India. The partnership also links Indian manufacturing with globally developed AI interconnect technology, creating a potential pathway from product development to commercial-scale production within the country.
“Once the ecosystem of chip designers, VCs and know-how is developed, it will help in achieving the long-term goal of the government, i.e., creation of fabless Indian companies. Semicon 2.0 provisions will help in achieving such a goal,” the Ministry of Electronics and Information Technology (MeitY) said in a statement to ET.
It further said Mixx’s acquisition of Sophic is “a good example of self-high value job creation and long-term tax benefits accruing out of it for the country. It reinforces the belief that Indian startups can build quality solutions.”
Sophic received electronic design automation (EDA) tools assistance from MeitY for chip design, which was also provided to the students of around 320 colleges.
Interconnect is key
Every major cloud provider is deploying advanced graphic processing units (GPUs) to boost compute capacity amid increasing AI adoption and data usage. However, raw compute density is only half the equation. The harder problem is making sure those GPUs are working to its full potential and not waiting, Raghuraman said.
In large AI clusters, accelerators spend a significant fraction of their time stalled on data waiting to move between chips fast enough to keep compute fed. The interconnect, not the GPU itself, is increasingly the binding constraint on utilisation. And utilisation directly determines the cost of a token and the energy burned to produce it.
For hyperscalers running inference at billions of queries a day, the economics are unforgiving: every percentage point of GPU idle time is waste at scale.
Introducing optics to declutter the data path improves efficiency.
Co-package optics (CPO), the most effective solution to the interconnect bottleneck, integrates photonic engines directly along with ASICs and accelerators, moving data at optical speeds and at a fraction of the power of conventional electrical interconnects. It unlocks the bandwidth density required to keep GPUs utilised efficiently and sustainably, bringing down both the cost of a token and the energy consumed to produce it.
Delivering CPO at hyperscale, however, requires precision across the full electronic-photonic stack; the hardest layer to design is the analogue mixed- signal interface between the photonics and the digital system. That is what Sophic has been designing at 7nm, 5nm, and 3nm process nodes.
Raghuraman said the market opportunity Mixx and Kaynes are targeting is expected to exceed $30 billion by 2030. Volumes could eventually reach 4-5 million units a year, and Kaynes is working towards building that capacity.
“To reach a capacity of about five million units per year, it will take about four years,” he said, adding that initial production would typically begin in the hundreds of thousands.
Mixx is in discussions with hyperscalers for adoption of its technology. Raghuraman said the company’s products are not necessarily competing directly with large chip companies such as Broadcom, Marvell, Intel, or Astera Labs, but could work alongside their ASICs and networking chips.
